The present invention generally relates to metal-oxide-semiconductor (MOS) devices and more particularly to a MOS device having the semiconductor-on-insulator (SOI) structure wherein the back channel effect is eliminated.
In conventional MOS transistors, the increase of operational speed of the device is limited because of the parasitic capacitance formed between the source/drain region and the substrate. In a MOS transistor having the SOI structure wherein a thin semiconductor layer acting as the substrate is provided on an insulator layer, such a parasitic capacitance is decreased significantly and a high speed operation can be achieved. Such a device also has a preferable feature of near-ideal isolation between the semiconductor devices and associated therewith, the device generally has a high breakdown voltage.
FIG. 1 shows a typical structure of the MOS transistor formed on an SOI substrate. Referring to the drawing, the SOI substrate includes a silicon wafer 40 and a silicon oxide layer 41 provided thereon. On the silicon oxide layer 41, there is formed a usual MOS transistor having a single crystal silicon substrate layer 42, source and drain regions 46 formed in the layer 42, a channel region 44 intervening between the source and drain regions 46, and a gate electrode 45 provided on the layer 42. The substrate layer 42 is isolated from the substrate layer of adjacent transistors by an isolation region 43 of silicon oxide. In the drawing, illustration of the gate insulation film is omitted.
Although such a structure is effective in reducing the parasitic capacitance, there arises a problem that a so-called back channel effect is tend to be caused. In the back channel effect, electric charges are accumulated at the interface between silicon substrate layer 42 and the silicon oxide layer 41 underneath, and such electric charges provide a back channel extending across the source and drain regions along the interface. In response to the appearance of the back channel effect, a leak current flows across the source and drain regions as illustrated by the arrow in FIG. 1.
As the back channel is an conductive inversion layer formed by the electric charges in the insulator layer 41, and the formation of the back channel can be reduced when the impurity concentration is increased. In other words, the back channel effect can be suppressed by increasing the impurity concentration of the semiconductor layer 42 acting as the substrate of the MOS transistor. For example, Japanese Laid-open Patent Application No. 58-64064 discloses a MOS transistor having the SOI structure wherein the semiconductor layer providing the channel region between the source and the drain regions is doped by ion implantation of impurities such that the concentration level of the impurities therein changes with three distinct concentration levels with the depth of the semiconductor layer. In this prior art, the concentration level adjacent to the insulator layer is maximized for eliminating the back channel effect.
Alternately, there is disclosed a similar technique for eliminating the back channel effect in the Japanese Laid-open Patent Application 60-220425. FIG. 2 shows the general feature of the MOS transistor disclosed in these prior art references. In such a MOS transistor, the channel region 44 is divided into the normal channel region 44a having a normal impurity concentration level and a back channel effect eliminating region 47 doped to an increased impurity concentration level. This region 47 is formed adjacent to the silicon oxide layer 41. Similarly to FIG. 1, the region 46 represents the source and drain regions and the region 45 represents the gate electrode.
In the MOS transistor of FIG. 2, the back channel effect is successfully eliminated as a result of the provision of the region 47. However, such a structure has a problem of poor breakdown characteristic because of the reason that the region 47 which is doped for example to the p-type with the high concentration level is located in contact with the source or drain region 46 which is doped to the n-type with the high concentration level. More specifically, such a device shows a decrease of the breakdown voltage to less than 10 volts when the region 47 is doped to the level of 2.times.10.sup.17 cm.sup.-3. In the usual device wherein the region 47 is not provided and the channel region 44 is doped in the level of 1.times.10.sup.16 cm.sup.-3, on the other hand, the breakdown voltage is usually about 50 volts.
Generally, the MOS integrated circuits are required to have a breakdown voltage which is about two times as large as the supply voltage in consideration of the noise in the supply voltage and the substrate biasing. As the supply voltage is usually set to 5 volts, the breakdown voltage of 10 volts or less is apparently insufficient.
Further, there is a known MOS transistor disclosed in the Japanese Laid-open Patent Application No. 62-104172 having an offset gate structure. The MOS transistor is constructed on a silicon single crystal layer provided on a silicon oxide substrate and has an isolated doped region having an increased impurity concentration level in the channel region formed in the silicon single crystal layer in correspondence to a boundary between the silicon oxide substrate and the silicon single crystal layer for eliminating the back channel effect. This isolated doped region is provided under an overhanging drain region characterizing the offset gate structure but is separated therefrom and further in an offset relationship with respect to the gate electrode provided on the silicon single crystal layer. Although this prior art MOS transistor can eliminate the back channel effect by the isolated doped region interrupting the formation of the inversion layer extending between the source and drain regions along the boundary to the underlying silicon oxide substrate, it has a problem in that a neutral region is formed in the channel region because of the relatively large thickness of the channel layer (about 0.5 .mu.m) which prevents the depletion region formed during the operation of the transistor from extending to and reaching the boundary to the underlying silicon oxide layer. When this occurs, there is a possibility that holes, which may be formed during the operation of the transistor as a result of impact ionization, are accumulated in the neutral region. In response thereto, the silicon single crystal layer is biased with respect to the source region and there appears a parasitic bipolar action in the parasitic bipolar transistor formed by the source region, drain region and the channel region intervening therebetween. When such a parasitic bipolar action occurs, a large amount of carriers are caused to flow between the source and drain regions and the breakdown voltage between the source and drain regions is significantly decreased. The MOS transistor of this reference is also disadvantageous from the viewpoint of forming a parasitic capacitance under the overhanging drain region which reduces the operational speed of the transistor. Further, such a MOS transistor having the offset gate structure occupies a large area and is disadvantageous from the view point of increasing the integration density of the integrated circuit. Furthermore, the resistance caused by the overhanging drain region provides an effect of reducing the operational speed.